K4B2G1646C-HCF8000 Datasheet, PDF (48/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
[ Table 50 ] Timing Parameters by Speed Bins for DDR3-1600 to DDR3-2133 (Cont.)
Speed
Parameter
Command and Address Timing
DLL locking time
Symbol
tDLLK
internal READ Command to PRECHARGE Command delay
tRTP
Delay from start of internal write transaction to internal read com-
mand
WRITE recovery time
Mode Register Set command cycle time
tWTR
tWR
tMRD
Mode Register Set command update delay
tMOD
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
tCCD
tDAL(min)
tMPRR
tRAS
ACTIVE to ACTIVE command period for 1KB page size
tRRD
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK referenced to
V_IH(AC) / V_IL(AC) levels
Command and Address hold time from CK, CK referenced to
V_IH(AC) / V_IL(AC) levels
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
tRRD
tFAW
tFAW
tIS(base)
AC175
tIS(base)
AC150
tIS(base)
AC135
tIS(base)
AC125
tIH(base)
DC100
tIPW
tZQinitI
Normal operation Full calibration time
tZQoper
Normal operation short calibration time
Reset Timing
tZQCS
Exit Reset from CKE HIGH to a valid command
tXPR
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked DLL
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit timing
Valid Clock Requirement after Self Refresh Entry (SRE) or Power-
Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit (SRX) or Power-
Down Exit (PDX) or Reset Exit
tXS
tXSDLL
tCKESR
tCKSRE
tCKSRX
DDR3-1600
MIN
MAX
DDR3-1866
MIN
MAX
DDR3-2133
MIN
MAX
512
-
512
-
512
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
15
-
15
-
15
-
4
-
4
-
4
-
max
(12nCK,15ns)
-
max
(12nCK,15ns)
-
max
(12nCK,15ns)
-
4
-
4
-
4
-
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42
max
(4nCK,6ns)
-
max
(4nCK, 5ns)
-
max
(4nCK, 5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK, 6ns)
-
max
(4nCK, 6ns)
-
30
-
27
-
25
-
40
-
35
-
35
-
45
-
-
-
-
-
45+125
-
-
-
-
-
-
-
65
-
60
-
-
-
150
-
135
-
120
-
100
-
95
-
560
-
535
-
470
-
512
-
max(512nCK,6
40ns)
-
max(512nCK,64
0ns)
-
256
-
max(256nCK,3
20ns)
-
max(256nCK,32
0ns)
-
64
-
max(64nCK,80
ns)
-
max(64nCK,80n
s)
-
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC(min) +
10ns)
-
max(5nCK,
tRFC(min) +
10ns)
-
max(5nCK,tRF
C + 10ns)
-
max(5nCK,tRF
C(min) + 10ns)
-
max(5nCK,tRFC
(min) + 10ns)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tCKE(min) +
1tCK
-
tCKE(min) +
1nCK
-
tCKE(min) +
1nCK
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Units
NOTE
nCK
e
e,18
ns
e
nCK
nCK
nCK
nCK
22
ns
e
e
e
ns
e
ns
e
ps
b,16
ps
b,16
ps
b,16
ps
b,16,27
ps
b,16
ps
28
nCK
nCK
nCK
23
nCK
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