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K4B2G1646C-HCF8000 Datasheet, PDF (13/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)
K4B2G1646C
datasheet
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
VIH.DIFF.AC.MIN
tDVAC
VIH.DIFF.MIN
Rev. 1.11
DDR3 SDRAM
0.0
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
half cycle
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Differential AC & DC Input Levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866/2133
min
max
unit
NOTE
VIHdiff
differential input high
+0.2
NOTE 3
V
1
VILdiff
differential input low
NOTE 3
-0.2
V
1
VIHdiff(AC)
differential input high ac
2 x (VIH(AC) - VREF)
NOTE 3
V
2
VILdiff(AC)
differential input low ac
NOTE 3
2 x (VIL(AC) - VREF)
V
2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low
level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,
VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)|
= 350mV
min
max
tDVAC [ps] @ |VIH/Ldiff(AC)|
= 300mV
min
max
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
tDVAC [ps] @ |VIH/Ldiff(AC)|
= 270mV
min
max
TBD
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tDVAC [ps] @ |VIH/Ldiff(AC)|
= 250mV
min
max
TBD
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TBD
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