K4B2G1646C-HCF8000 Datasheet, PDF (33/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
[ Table 37 ] IDD4W Measurement - Loop Pattern¹⁾
Rev. 1.11
DDR3 SDRAM
0
0
WR
0
1
0
0
1
0 00 0
0
0
0
1
D
1
0
0
0
1
0 00 0
0
0
0
2,3
D,D
1
1
1
1
1
0 00 0
0
0
0
4
WR
0
1
0
0
1
0 00 0
0
F
0
5
D
1
0
0
0
1
0 00 0
0
F
0
6,7
D,D
1
1
1
1
1
0 00 0
0
F
0
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
[ Table 38 ] IDD5B Measurement - Loop Pattern¹⁾
00000000
-
-
00110011
-
-
0
0
REF
0
0
0
1
0
0 00 0
0
0
0
-
1
1,2
D
1
0
0
0
0
0 00 0
0
0
0
-
3,4
D,D
1
1
1
1
0
0 00 0
0
F
0
-
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
2
33...nRFC - 1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
NOTE :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
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