K4B2G1646C-HCF8000 Datasheet, PDF(12/64 Page) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

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K4B2G1646C-HCF8000 Datasheet, PDF (12/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

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K4B2G1646C

datasheet

Rev. 1.11

DDR3 SDRAM

8.2 VREF Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage

VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).

VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on

page 11. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than Â± 1% VDD.

voltage

VDD

VSS

time

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.

"VREF" shall be understood as VREF(DC), as defined in Figure 1 .

This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing

and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

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