K4B2G1646C-HCF8000 Datasheet, PDF (16/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
9. AC & DC Output Measurement Levels
9.1 Single-ended AC & DC Output Levels
[ Table 14 ] Single-ended AC & DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866/2133
Units NOTE
V_OH(DC)
V_OM(DC)
V_OL(DC)
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
0.8 x V_DDQ
V
0.5 x V_DDQ
V
0.2 x V_DDQ
V
V_OH(AC)
AC output high measurement level (for output SR)
V_TT + 0.1 x V_DDQ
V
1
V_OL(AC)
AC output low measurement level (for output SR)
V_TT - 0.1 x V_DDQ
V
1
NOTE : 1. The swing of +/-0.1 x V_DDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to V_TT=V_DDQ/2.
9.2 Differential AC & DC Output Levels
[ Table 15 ] Differential AC & DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600/1866/2133
Units
NOTE
V_OHdiff(AC) AC differential output high measurement level (for output SR)
+0.2 x V_DDQ
V
1
V_OLdiff(AC) AC differential output low measurement level (for output SR)
-0.2 x V_DDQ
V
1
NOTE : 1. The swing of +/-0.2xV_DDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
load of 25Ω to V_TT=V_DDQ/2 at each of the differential outputs.
9.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OL(AC) and V_OH(AC)
for single ended signals as shown in Table 16 and Figure 6.
[ Table 16 ] Single-ended output slew rate definition
Description
Measured
From
To
Defined by
Single ended output slew rate for rising edge
V_OL(AC)
V_OH(AC)
V_OH(AC)-V_OL(AC)
Delta TRse
Single ended output slew rate for falling edge
V_OH(AC)
V_OL(AC)
V_OH(AC)-V_OL(AC)
Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single-ended output slew rate
Parameter
Symbol
DDR3-800
Min Max
DDR3-1066
Min Max
DDR3-1333
Min Max
DDR3-1600
Min Max
DDR3-1866
Min Max
DDR3-2133
Units
Min Max
Single ended output slew rate SRQse 2.5
5
2.5
5
2.5
5
2.5
5
2.5
5¹⁾
2.5
5^{1) V/ns}
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
V_OH(AC)
V_TT
V_OL(AC)
delta TFse
delta TRse
Figure 6. Single-ended Output Slew Rate Definition
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