K4B2G1646C-HCF8000 Datasheet, PDF (22/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
tion, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that V_DDQ = V_DD and that V_SSQ = V_SS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV_DDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g.
calibration at 0.2XV_DDQ and 0.8XV_DDQ.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply V_IH(AC) to pin under test and measure current I(V_IH(AC)), then apply V_IL(AC) to pin under test and measure current I(V_IL(AC)) respectively
RTT =
V_IH(AC) - V_IL(AC)
I(V_IH(AC)) - I(V_IL(AC))
6. Measurement definition for V_M and ∆V_M : Measure voltage (V_M) at test pin (midpoint) with no load
∆ V_M =
2 x V_{M - 1 x 100}
V_DDQ
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
∆T = T - T(@calibration); ∆V = V_DDQ - V_DDQ (@calibration); V_DD = V_DDQ
[ Table 26 ] ODT Sensitivity Definition
RTT
Min
0.9 - dR_TTdT * |∆T| - dR_TTdV * |∆V|
Max
1.6 + dR_TTdT * |∆T| + dR_TTdV * |∆V|
[ Table 27 ] ODT Voltage and Temperature Sensitivity
Min
dR_TTdT
0
dR_TTdV
0
NOTE : These parameters may not be subject to production test. They are verified by design and characterization.
Max
1.5
0.15
Units
RZQ/2,4,6,8,12
Units
%/°C
%/mV
- 22 -