K4B2G1646C-HCF8000 Datasheet, PDF (26/64 Pages) Samsung semiconductor – 2Gb C-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant)

K4B2G1646C
datasheet
Rev. 1.11
DDR3 SDRAM
10. IDD Current Measure Method
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all V_DD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V_DDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V_DD and V_DDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as V_IN <= V_ILAC(max).
- "1" and "HIGH" is defined as V_IN >= V_IHAC(min).
- "FLOATING" is defined as inputs are V_REF = V_DD / 2.
- "Timing used for IDD and IDDQ Measured - Loop Patterns" are provided in Table 30
- "Basic IDD and IDDQ Measurement Conditions" are described in Table 31
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 31 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
- RESET Stable time is : During a Cold Bood RESET (Initialization), current reading is valid once power is stable and RESET has been LOW for 1ms;
During Warm Boot RESET(while operating), current reading is valid after RESET has been LOW for 200ns + tRFC
[ Table 30 ] Timing used for IDD and IDDQ Measured - Loop Patterns
Parameter Bin
DDR3-800
6-6-6
DDR3-1066
7-7-7
DDR3-1333
9-9-9
tCKmin(IDD)
2.5
1.875
1.5
CL(IDD)
6
7
9
tRCDmin(IDD)
6
7
9
tRCmin(IDD)
21
27
33
tRASmin(IDD)
15
20
24
tRPmin(IDD)
6
7
9
x4/x8
16
20
20
tFAW(IDD)
x16
20
27
30
x4/x8
4
4
4
tRRD(IDD)
x16
4
6
5
tRFC(IDD) - 512Mb
36
48
60
tRFC(IDD) - 1Gb
44
59
74
tRFC(IDD) - 2Gb
64
86
107
tRFC(IDD) - 4Gb
120
160
200
tRFC(IDD) - 8Gb
140
187
234
DDR3-1600
11-11-11
1.25
11
11
39
28
11
24
32
5
6
72
88
128
240
280
DDR3-1866
13-13-13
1.07
13
13
45
32
13
26
33
5
6
85
103
150
281
328
DDR3-2133
Unit
14-14-14
0.935
ns
14
nCK
14
nCK
50
nCK
36
nCK
14
nCK
27
nCK
38
nCK
6
nCK
7
nCK
97
nCK
118
nCK
172
nCK
321
nCK
375
nCK
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