H8SX1544 Datasheet, PDF (968/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

TMDR..........................320, 842, 861, 875
TSR..................................................... 425
TSR (TPU)...................342, 842, 861, 875
TSTR ...........................347, 842, 861, 874
TSYR...........................348, 842, 861, 874
TXACK0 .....................564, 820, 844, 863
TXCR0 ........................563, 820, 844, 863
TXPR0.........................560, 820, 844, 863
TXPR1.........................560, 820, 844, 863
UMSR0........................569, 820, 844, 863
VBR...................................................... 32
WTCNT .......................406, 835, 849, 867
WTCOR.......................410, 835, 849, 867
WTCR..........................407, 835, 849, 867
WTCRA.......................136, 839, 856, 871
WTCRB.......................136, 839, 856, 871
WTSR ..........................408, 835, 849, 867
Repeat transfer mode .............................. 217
Reset ......................................................... 82
Reset state................................................. 64
Resolution............................................... 643
Rewrite of CKS2 to CKS0...................... 686
Rewriting bits CKS2 to CKS0 ................ 416
Rewriting PSS bit ................................... 416
S
Sample-and-hold circuit ......................... 641
Scan mode .............................................. 639
Serial communication interface (SCI) .... 419
Single address mode ............................... 214
Single mode ............................................ 638
Slave receive mode................................. 515
Slave transmit mode ............................... 512
Sleep mode ............................. 572, 798, 808
Smart card interface................................ 472
Software protection................................. 751
Software standby mode .................. 798, 809
Sound generator (SDG) .......................... 687
SSU mode............................................... 611
Rev.2.00 Oct. 16, 2007 Page 914 of 916
REJ09B0381-0200
Stack status after exception handling........ 91
Standard serial communication interface
specifications for boot mode ................... 756
Start bit.................................................... 448
State transitions......................................... 65
Stop bit.................................................... 448
Strobe assert/negate timing ..................... 157
Sub-Clock Mode ..................................... 798
Switching between 16-bit PWM mode
and 10-bit stepping motor mode ............. 686
Switching between compare match timer
and interval timer modes......................... 416
Synchronous clearing.............................. 355
Synchronous operation............................ 355
Synchronous presetting........................... 355
Synchronous serial communication unit
(SSU) ...................................................... 589
System clock (Iφ) ............................ 149, 785
T
Test mode settings .................................. 575
The address map for each mailbox ......... 529
Time quanta is defined............................ 546
Toggle output.......................................... 352
Tone frequency setting............................ 698
Trace exception handling .......................... 85
Transfer clock ......................................... 607
Transmit/receive data.............................. 448
Trap instruction exception handling ......... 89
U
User program mode ........................ 705, 737
V
Vector table address.................................. 80
Vector table address offset........................ 80