H8SX1544 Datasheet, PDF (370/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Bit 7
Bit 6
Bit 5
Channel Reserved*² CCLR1 CCLR0
Description
1, 2, 4, 5 0
0
0
TCNT clearing disabled
0
0
1
TCNT cleared by TGRA compare match/input
capture
0
1
0
TCNT cleared by TGRB compare match/input
capture
0
1
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*¹
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Table 9.5 Input Clock Edge Selection
Clock Edge Selection
CKEG1
CKEG0
0
0
0
1
1
×
Legend:
×: Don't care
Internal Clock
Counted at falling edge
Counted at rising edge
Counted at both edges
Input Clock
External Clock
Counted at rising edge
Counted at falling edge
Counted at both edges
Rev.2.00 Oct. 16, 2007 Page 316 of 916
REJ09B0381-0200