H8SX1544 Datasheet, PDF (765/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 22 Flash Memory
22.5 Input/Output Pins
The flash memory is controlled through the input/output pins shown in table 22.2.
Table 22.2 Pin Configuration
Abbreviation
RES
MD2 to MD0
TxD4
RxD4
I/O
Input
Input
Output
Input
Function
Reset
Set operating mode of this LSI
Serial transmit data output (used in boot mode)
Serial receive data input (used in boot mode)
22.6 Register Descriptions
The flash memory has the following registers.
Programming/Erasing Interface Registers:
• Flash code control/status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash transfer destination address register (FTDAR)
Programming/Erasing Interface Parameters:
• Download pass and fail result parameter (DPFR)
• Flash pass and fail result parameter (FPFR)
• Flash program/erase frequency parameter (FPEFEQ)
• Flash multipurpose address area parameter (FMPAR)
• Flash multipurpose data destination area parameter (FMPDR)
• Flash erase block select parameter (FEBS)
• Flash user branch address set parameter (FUBRA)
• RAM emulation register (RAMER)
There are several operating modes for accessing the flash memory. Respective operating modes,
registers, and parameters are assigned to the user MAT. The correspondence between operating
modes and registers/parameters for use is shown in table 22.3.
Rev.2.00 Oct. 16, 2007 Page 711 of 916
REJ09B0381-0200