H8SX1544 Datasheet, PDF (805/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 22 Flash Memory
22.8.2 Software Protection
The software protection protects the flash memory against programming/erasing by disabling
download of the programming/erasing program, using the key code, and by the RAMER setting.
Table 22.11 Software Protection
Function to Be Protected
Item
Description
Download
Programming/
Erasing
Protection The programming/erasing protection state is
O
O
by SCO bit entered when the SCO bit in FCCS is cleared to 0
to disable download of the programming/erasing
programs.
Protection The programming/erasing protection state is
O
O
by FKEY entered because download and
programming/erasing are disabled unless the
required key code is written in FKEY.
Emulation The programming/erasing protection state is
O
O
protection entered when the RAMS bit in the RAM emulation
register (RAMER) is set to 1.
22.8.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when a CPU runaway
occurs or operations not according to the programming/erasing procedures are detected during
programming/erasing of the flash memory. Aborting programming or erasure in such cases
prevents damage to the flash memory due to excessive programming or erasing.
If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set
to 1 and the error protection state is entered.
• When an interrupt request, such as NMI, occurs during programming/erasing.
• When the flash memory is read from during programming/erasing (including a vector read or
an instruction fetch).
• When a SLEEP instruction is executed (including software-standby mode) during
programming/erasing.
• When a bus master other than the CPU, such as the DMAC, obtains bus mastership during
programming/erasing.
Rev.2.00 Oct. 16, 2007 Page 751 of 916
REJ09B0381-0200