H8SX1544 Datasheet, PDF (300/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 7 DMA Controller (DMAC)
(2) Single Address Mode (Write and Cycle Stealing)
In single address mode, data of one byte, one word, or one longword is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU are executed in the bus released cycles.
In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (write).
Bφ
Address bus
LLWR
DACK
TEND
DMA write
cycle
DMA write
cycle
DMA write
cycle
DMA write
cycle
Bus
released
Bus
released
Bus
released
Bus ^{Last transfer Bus}
released
cycle released
Figure 7.34 Example of Transfer in Single Address Mode (Byte Write)
Rev.2.00 Oct. 16, 2007 Page 246 of 916
REJ09B0381-0200