H8SX1544 Datasheet, PDF (165/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

A block diagram of interrupts IRQn is shown in figure 5.2.
Section 5 Interrupt Controller
Corresponding bit
in ICR
Input buffer
IRQn input
IRQnSF, IRQnSR
Edge/level
detection circuit
IRQnE
IRQnF
S
Q
R
IRQn interrupt request
Note: n = 15 to 0
Clear signal
Figure 5.2 Block Diagram of Interrupts IRQn
When ISCR is set so that an IRQn interrupt request is generated at IRQn low-level input, IRQn
input should be held low until interrupt handling starts. Then set the corresponding input signal
IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be
executed when the corresponding input signal IRQn is set to high before the interrupt handling
begins.
5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
• The interrupt priority can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, or other interrupt request.
• The priority level of DMAC activation can be controlled by the DMAC priority control
functions.
Rev.2.00 Oct. 16, 2007 Page 111 of 916
REJ09B0381-0200