H8SX1544 Datasheet, PDF (808/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 22 Flash Memory
Figure 22.16 shows an example of overlaying flash memory block area EB0.
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
Flash memory
user MAT
EB8 to EB15
H'7FFFF
This area can be accessed via
both the on-chip RAM and flash
memory area.
H'FF6000
H'FFA000
H'FFAFFF
On-chip RAM
H'FFBFFF
Figure 22.16 Address Map of Overlaid RAM Area
The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in
RAMER from among the eight blocks, EB0 to EB7, of the user MAT.
To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in
RAMER to 1 and bits RAM2 to RAM0 to B'000.
For programming/erasing the user MAT, the procedure programs including a download program
of the on-chip program must be executed. At this time, the download area should be specified so
that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area
in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the
tuned data must be saved in an unused area beforehand.
Rev.2.00 Oct. 16, 2007 Page 754 of 916
REJ09B0381-0200