H8SX1544 Datasheet, PDF(625/974 Page) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

H8SX1544 Datasheet, PDF (625/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

◁

Power On/Software Reset*1

Configuration Mode

MCR[0] = 1

(automatically in hardware reset only)

IRR[0] = 1, GSR[3] = 1 (automatically)

clear IRR[0] Bit

Configure MCR[15]

RCAN-ET Timer Reg Setting

Mailbox Setting

(STD-ID, EXT-ID, LAFM, DLC,

RTR, IDE, MBC, MBIMR, DART,

ATX, NMC, Message-Data)*2

Set Bit Timing (BCR)

Clear MCR[0]

Section 14 Controller Area Network (RCAN-ET)

GSR[3] = 0?

Yes

No*3

RCAN-ET is

in Transmit/Receive Mode

Set TXPR to start transmission

or stay idle to receive

Transmit/Receive mode

Detect 11 recessive bits and

Join the CAN bus activity

Receive*4

Transmit*4

Notes: 1. Software reset could be performed at any time by setting MCR[0] = 1.

2. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC.

3. It takes approximately 25 peripheral bus cycles for GSR[3] to be cleared to 0.

4. If there is no TXPR set, RCAN-ET will receive the next incoming message.

If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.

If it loses the arbitration, it will become a receiver.

Figure 14.6 Reset Sequence

Rev.2.00 Oct. 16, 2007 Page 571 of 916

REJ09B0381-0200

▷