H8SX1544 Datasheet, PDF (258/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 7 DMA Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
2
DMAP2 0
R/W DMA Priority Level 2 to 0
1
DMAP1 0
0
DMAP0 0
R/W Select the priority level of the DMAC. When the CPU
R/W
has priority over the DMAC, the DMAC masks a transfer
request and waits for the timing when the CPU priority
becomes lower than the DMAC priority. The priority
levels can be set to the individual channels. This bit is
valid when the CPUPCE bit in CPUPCR is set to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)
Note: * Only 0 can be written to, to clear the flag.
Rev.2.00 Oct. 16, 2007 Page 204 of 916
REJ09B0381-0200