H8SX1544 Datasheet, PDF (666/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 15 Synchronous Serial Communication Unit (SSU)
(2) Data Transmission
Figure 15.5 shows an example of transmission operation, and figure 15.6 shows a flowchart
example of data transmission.
When transmitting data, the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal
is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in
synchronization with the transfer clock.
Writing transmit data to SSTDR after the completion of the initial setting clears the TDRE bit in
SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the
TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI
interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the
SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
Rev.2.00 Oct. 16, 2007 Page 612 of 916
REJ09B0381-0200