H8SX1544 Datasheet, PDF (272/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 7 DMA Controller (DMAC)
(3) Block Transfer Mode
In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4
Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR
up to 65536 × data access size.
While one block of data is being transferred, transfer requests from other channels are suspended.
When the transfer is completed, the bus is released to the other bus master.
The block area can be specified for the source or destination address side by bits ARS1 and ARS0
in DACR. The address specified as the block area returns to the transfer start address when the
block size of data is completed. When the block area is specified as neither source nor destination
address side, the operation continues without returning the address to the transfer start address. A
repeat size end interrupt can be requested.
The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle.
When the external request is selected as an activation source, the low level detection of the DREQ
signal (DREQS = 0) should be selected.
When an interrupt request by an extended repeat area overflow is used in block transfer mode,
settings should be selected carefully. For details, see section 7.5.5, Extended Repeat Area
Function.
Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer
conditions are as follows:
• Address mode: single address mode
• Data access size: byte
• 1-block size: three bytes
The block transfer mode operations in single address mode and in dual address mode are shown in
figures 7.11 and 7.12, respectively.
DREQ
Bus cycle
TEND
CPU CPU
Transfer cycles for one block
DMAC DMAC DMAC
No CPU cycle generated
CPU
Figure 7.10 Operations in Block Transfer Mode
Rev.2.00 Oct. 16, 2007 Page 218 of 916
REJ09B0381-0200