H8SX1544 Datasheet, PDF (434/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
(2) Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 9.32 shows output compare output timing.
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare match
signal
TIOC pin
Figure 9.32 Output Compare Output Timing
(3) Input Capture Signal Timing
Figure 9.33 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 9.33 Input Capture Input Signal Timing
Rev.2.00 Oct. 16, 2007 Page 380 of 916
REJ09B0381-0200