H8SX1544 Datasheet, PDF (620/974 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family/H8SX/1500 Series

Section 14 Controller Area Network (RCAN-ET)
14.5.5 Data Frame Receive Pending Register 0 (RXPR0)
The RXPR0 is a 16-bit read / conditionally-write registers. The RXPR is a register that contains
the received Data Frames pending flags associated with the configured Receive Mailboxes. When
a CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox
Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame
Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the
interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving
Data Frames and not by receiving Remote frames.
• RXPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a '1' to clear.
Bits 15 to 0: Configurable receive mailbox locations corresponding to each mailbox position from
15 to 0 respectively.
Bit[15:0]: RXPR0
0
1
Description
[Clearing condition] Writing '1' (Initial value)
When clearing this flag by the CPU in the interrupt handling, always read it
after writing ‘1’ to it.
Corresponding Mailbox received a CAN Data Frame
[Setting condition] Completion of Data Frame receive on corresponding
mailbox
Rev.2.00 Oct. 16, 2007 Page 566 of 916
REJ09B0381-0200