4554 Datasheet, PDF (96/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction
code
D9
D0
Number of
1
0
0
1
1
1
0
0
1
0
2
2
7
2 ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T37–T34)
(A) ← (T33–T30)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T37–T34) of
timer 3 to register B.
Transfers the low-order 4 bits (T33–T30) of
timer 3 to register A.
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction
code
D9
D0
Number of
1
0
0
1
1
1
0
0
1
1
2
2
7
3 ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T47–T44)
(A) ← (T43–T40)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of
0000101010
02A
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
D0
Number of Number of Flag CY
0
0
1
0
p5 p4 p3 p2 p1 p0 0
2
8
+p
p
16
words
1
cycles
3
–
Skip condition
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping: Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by reg-
isters A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Note: p is 0 to 63 for M34554M8, and p is 0 to 95 for M34554MC, and p is 0 to 127 for M34554ED.
When this instruction is executed, be careful not to over the stack because 1 stage of
stack register is used.
Rev.3.00 Aug 06, 2004 page 96 of 136
REJ03B0043-0300Z