4554 Datasheet, PDF (67/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
CONTROL REGISTERS
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 External 1 interrupt enable bit
V10 External 0 interrupt enable bit
Interrupt control register V2
V23 ^{Timer 4 interrupt enable bit}
V22 ^{Not used}
V21 ^{Timer 5 interrupt enable bit}
V20 ^{Timer 3 interrupt enable bit}
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT4 instruction is valid)
1
Interrupt enabled (SNZT4 instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZT5 instruction is valid)
1
Interrupt enabled (SNZT5 instruction is invalid)
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV1/TV1A
R/W
TAV2/TV2A
Interrupt control register I1
I13 INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
I12
return level selection bit (Note 2)
I11 INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
I10
circuit selection bit
at reset : 00002
at power down : state retained
R/W
TAI1/TI1A
0
INT0 pin input disabled
1
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Interrupt control register I2
I23 INT1 pin input control bit (Note 2)
at reset : 00002
at power down : state retained
0
INT1 pin input disabled
1
INT1 pin input enabled
R/W
TAI2/TI2A
Interrupt valid waveform for INT1 pin/
I22
return level selection bit (Note 2)
Falling waveform/“L” level (“L” level is recognized with the SNZI1
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
1
instruction)
I21 INT1 pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT1 pin Timer 3 count start synchronous
I20
circuit selection bit
0
Timer 3 count start synchronous circuit not selected
1
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
Rev.3.00 Aug 06, 2004 page 67 of 136
REJ03B0043-0300Z