4554 Datasheet, PDF (59/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
PU03
PU02
PU01
PU00
Pull-up control register PU0
Port P03 pull-up transistor
control bit
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
PU13
PU12
PU11
PU10
Pull-up control register PU1
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
Interrupt control register I1
I13 INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
I12
return level selection bit (Note 2)
I11 INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
I10
circuit selection bit
at reset : 00002
at power down : state retained
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
at reset : 00002
at power down : state retained
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
R/W
TAPU0/
TPU0A
R/W
TAPU1/
TPU1A
at reset : 00002
at power down : state retained
0
INT0 pin input disabled
R/W
TAI1/TI1A
1
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Interrupt control register I2
I23 INT1 pin input control bit (Note 2)
at reset : 00002
at power down : state retained
0
INT1 pin input disabled
1
INT1 pin input enabled
R/W
TAI2/TI2A
Interrupt valid waveform for INT1 pin/
I22
return level selection bit (Note 2)
Falling waveform/“L” level (“L” level is recognized with the SNZI1
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
1
instruction)
I21 INT1 pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT1 pin Timer 3 count start synchronous
I20
circuit selection bit
0
Timer 3 count start synchronous circuit not selected
1
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set.
Rev.3.00 Aug 06, 2004 page 59 of 136
REJ03B0043-0300Z