4554 Datasheet, PDF (33/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
On-chip oscillator
(CMCK)
Ceramic resonance
XI N
RC oscillation
Multi-
plexer
(CRCK)
(CMCK/CRCK)
(Note 1)
XCIN
Quartz-crystal
oscillation
D7/CNTR0
W 60
0
1
Port D7 output
W 23
0
1
M R0
0
1
1/2
1/2
Division circuit
Divided by 8
Divided by4
Divided by 2
T1UDF
T2UDF
D8/INT0
I13
I10
I12
Falling
0
One-sided edge
detection circuit
1
Rising
Both edges
detection circuit
I11
0 ^{(Note 2)}
SQ
1
R
MR3, MR2
11
10
01
00
System clock (STCK)
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
PA0 (Note 4)
0
1
Prescaler (8)
ORCLK
(TABPS)
Reload register RPS (8)
(TPSAB) _(TPSAB) (TPSAB)
Register B Register A
(TABPS)
I10
1
0
W13
T1UDF
INSTCK
ORCLK
T5UDF
D7/CNTR0
W11, W10
00
01
10
11
(Note 4)
W12
0
1
Timer 1 (8)
(TAB1)
Reload register R1 (8)
(T1AB) (TR1AB) (T1AB)
(T1AB)
Register B Register A
(TAB1)
Timer 1
T1F
interrupt
Timer 1 underflow signal (T1UDF)
STCK
ORCLK
T1UDF
PWMOUT
W21, W20
00
01
10
11
(Note 4)
W22
0
1
Timer 2 (8)
(TAB2)
Reload register R2 (8)
(T2AB) _(T2AB) (T2AB)
Register B Register A
(TAB2)
Timer 2
T2F _interrupt
Timer 2 underflow signal (T2UDF)
D9/INT1
I23
I20
W33
T3UDF
PWMOUT
ORCLK
T2UDF
C/CNTR1
W31, W30
00
01
10
11
I22
Falling One-sided edge
0
detection circuit
I21
0 ^{(Note 3)}
I20
SQ
1
1
Both edges
1
0
Rising detection circuit
R
(Note 4)
W32
0
1
Timer 3 (8)
(TAB3)
Reload register R3 (8)
(T3AB) (TR3AB) (T3AB)
(T3AB)
Register B Register A
(TAB3)
Timer 3
T3F interrupt
Timer 3 underflow signal (T3UDF)
T5UDF: Timer 5 underflow signal (from timer 5)
PWMOUT: PWM output signal (from timer 4 output unit)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 1: When CMCK instruction is executed, ceramic resonance is selected.
When CRCK instruction is executed, RC oscillation is selected.
When any instructions are not executed, on-chip oscillator clock
(internal oscillation) is selected.
2: Timer 1 count start synchronous circuit is set
by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12)
of register I1.
3: Timer 3 count start synchronous circuit is set
by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22)
of register I2.
4: Count source is stopped by clearing to “0.”
Fig. 25 Timer structure (1)
Rev.3.00 Aug 06, 2004 page 33 of 136
REJ03B0043-0300Z