4554 Datasheet, PDF (25/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
System clock
(STCK)
1 machine cycle
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
Interrupt enable
flag (INTE)
EI instruction execution cycle
Interrupt enabled state
Interrupt disabled state
External
interrupt
INT0,INT1
EXF0,EXF1
Timer 1,
Timer 2,
Timer 3,
Timer 4,
Timer 5
interrupts
T1F,T2F,T3F,
T4F,T5F
Interrupt activated
condition is satisfied.
Retaining level of system
clock for 4 periods or more
is necessary.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
The program starts
from the interrupt
address.
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
Rev.3.00 Aug 06, 2004 page 25 of 136
REJ03B0043-0300Z