4554 Datasheet, PDF (53/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
(2) Internal state at reset
Figure 40 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 40 are undefined, so set the ini-
tial value to them.
• Program counter (PC) ............................................................................0.......0......0......0.......0.... 0 0 0 0 0 0 0 0 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0 (Interrupt disabled)
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 .................................................................................0......0.......0.... 0 (Interrupt disabled)
• Interrupt control register V2 .................................................................................0......0.......0.... 0 (Interrupt disabled)
• Interrupt control register I1 ..................................................................................0......0.......0.... 0
• Interrupt control register I2 ..................................................................................0......0.......0.... 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Timer 4 interrupt request flag (T4F) ..................................................................................... 0
• Timer 5 interrupt request flag (T5F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0 (Prescaler stopped)
• Timer control register W1 ....................................................................................0......0.......0.... 0 (Timer 1 stopped)
• Timer control register W2 ....................................................................................0......0.......0.... 0 (Timer 2 stopped)
• Timer control register W3 ....................................................................................0......0.......0.... 0 (Timer 3 stopped)
• Timer control register W4 ....................................................................................0......0.......0.... 0 (Timer 4 stopped)
• Timer control register W5 ....................................................................................0......0.......0.... 0 (Timer 5 stopped)
• Timer control register W6 ....................................................................................0......0.......0.... 0 (Timer LC stopped)
• Clock control register MR ....................................................................................1......1.......0.... 0
• LCD control register L1 .......................................................................................0......0.......0.... 0
• LCD control register L2 .......................................................................................0......0.......0.... 0
• LCD control register L3 .......................................................................................0......0.......0.... 0
• Key-on wakeup control register K0 .....................................................................0......0.......0.... 0
• Key-on wakeup control register K1 .....................................................................0......0.......0.... 0
• Key-on wakeup control register K2 .....................................................................0......0.......0.... 0
• Pull-up control register PU0 ................................................................................0......0.......0.... 0
• Pull-up control register PU1 ................................................................................0......0.......0.... 0
• Port output structure control register FR0 ..........................................................0......0.......0.... 0
• Port output structure control register FR1 ..........................................................0......0.......0.... 0
• Port output structure control register FR2 ..........................................................0......0.......0.... 0
• Carry flag (CY) ...................................................................................................................... 0
• Register A ............................................................................................................0......0.......0.... 0
• Register B ............................................................................................................0......0.......0.... 0
• Register D ..................................................................................................................✕.......✕.... ✕
• Register E ..................................................................................✕.......✕......✕.......✕......✕......✕.......✕.... ✕
• Register X ............................................................................................................0......0.......0.... 0
• Register Y ............................................................................................................0......0.......0.... 0
• Register Z .........................................................................................................................✕.... ✕
• Stack pointer (SP) .....................................................................................................1.......1.... 1
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
• Quartz-crystal oscillator ........................................................................................ Operating
“✕” represents undefined.
Fig. 40 Internal state at reset
Rev.3.00 Aug 06, 2004 page 53 of 136
REJ03B0043-0300Z