4554 Datasheet, PDF (65/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
17 _{D9/INT1 pin}
❶ Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in software, be careful about the following notes.
❸ Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the fol-
lowing notes.
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 57➀)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
57➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 57➂).
• Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 59➀)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
59➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 59➂).
LA 4
TV1A
LA 8
TI2A
NOP
SNZ1
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT1 pin input is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
LA 4
TV1A
LA 12
TI2A
NOP
SNZ1
NOP
; (✕✕0✕2)
; The SNZ1 instruction is valid ........... ➀
; (✕1✕✕2)
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ1 instruction is executed
(EXF1 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
Fig. 57 External 1 interrupt program example-1
✕ : these bits are not used here.
Fig. 59 External 1 interrupt program example-3
❷ Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to “0”, the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
• When the key-on wakeup function of INT1 pin is not used (regis-
ter K22 = “0”), clear bits 2 and 3 of register I2 before system
enters to the RAM back-up mode. (refer to Figure 58➀).
LA 0
TI2A
DI
EPOF
POF2
; (00✕✕2)
; Input of INT1 disabled ..................... ➀
; RAM back-up
✕ : these bits are not used here.
Fig. 58 External 1 interrupt program example-2
Rev.3.00 Aug 06, 2004 page 65 of 136
REJ03B0043-0300Z