4554 Datasheet, PDF (24/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The timer 3, timer 5, timer 4 interrupt enable bit is assigned to
register V2. Set the contents of this register through register A
with the TV2A instruction. The TAV2 instruction can be used to
transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 External 1 interrupt enable bit
V10 External 0 interrupt enable bit
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
R/W
TAV1/TV1A
Interrupt control register V2
at reset : 00002
at power down : 00002
0
V23 Timer 4 interrupt enable bit
1
0
V22 Not used
1
0
V21 Timer 5 interrupt enable bit
1
0
V20 Timer 3 interrupt enable bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV2/TV2A
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20, V21, V23), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt
conditions are satisfied on execution of other than one-cycle in-
structions (Refer to Figure 16).
Rev.3.00 Aug 06, 2004 page 24 of 136
REJ03B0043-0300Z