4554 Datasheet, PDF (6/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
MULTIFUNCTION
Pin
Multifunction
C
D7
D8
D9
VLC3
VLC2
VLC1
CNTR1
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
Pin
CNTR1
CNTR0
INT0
INT1
SEG0
SEG1
SEG2
Multifunction
C
D7
D8
D9
VLC3
VLC2
VLC1
Pin
P20
P21
P22
P23
P30
P31
P32
P33
Multifunction
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
Notes 1: Pins except above have just single function.
2: The output of D8 and D9 can be used even when INT0 and INT1 are selected.
3: The input/output of D7 can be used even when CNTR0 (input) is selected.
4: The input of D7 can be used even when CNTR0 (output) is selected.
5: The port C “H” output function can be used even when CNTR1 (output) is selected.
Pin
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
Multifunction
P20
P21
P22
P23
P30
P31
P32
P33
DEFINITION OF CLOCK AND CYCLE
q Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
Table Selection of system clock
Register MR
System clock
MR3 MR2 MR1 MR0
0
0
0
0 f(STCK) = f(XIN) or f(RING)
0 or 1 1 f(STCK) = f(XCIN)
0
1
0
0 f(STCK) = f(XIN)/2 or f(RING)/2
0 or 1 1 f(STCK) = f(XCIN)/2
1
0
0
0 f(STCK) = f(XIN)/4 or f(RING)/4
0 or 1 1 f(STCK) = f(XCIN)/4
1
1
0
0 f(STCK) = f(XIN)/8 or f(RING)/8
0 or 1 1 f(STCK) = f(XCIN)/8
Note: The f(RING)/8 is selected after system is released from reset.
q System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
q Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle gen-
erates the one machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
High-speed through mode
Low-speed through mode
High-speed frequency divided by 2 mode
Low-speed frequency divided by 2 mode
High-speed frequency divided by 4 mode
Low-speed frequency divided by 4 mode
High-speed frequency divided by 8 mode
Low-speed frequency divided by 8 mode
Rev.3.00 Aug 06, 2004 page 6 of 136
REJ03B0043-0300Z