4554 Datasheet, PDF (27/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to D8/INT0 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
(2) External 1 interrupt request flag (EXF1)
External 1 interrupt request flag (EXF1) is set to “1” when a valid
waveform is input to D9/INT1 pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
The state of EXF1 flag can be examined with the skip instruction
(SNZ1). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF1 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to D8/INT0 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
• External 1 interrupt activated condition
External 1 interrupt activated condition is satisfied when a valid
waveform is input to D9/INT1 pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 1 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT0 pin to be in the in-
put enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
➀ Set the bit 3 of register I2 to “1” for the INT1 pin to be in the in-
put enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I2.
➂ Clear the EXF1 flag to “0” with the SNZ1 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ1 instruction.
➄ Set both the external 1 interrupt enable bit (V11) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the D8/INT0 pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
The external 1 interrupt is now enabled. Now when a valid wave-
form is input to the D9/INT1 pin, the EXF1 flag is set to “1” and the
external 1 interrupt occurs.
Rev.3.00 Aug 06, 2004 page 27 of 136
REJ03B0043-0300Z