4554 Datasheet, PDF (46/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
LCD FUNCTION
The 4554 Group has an LCD (Liquid Crystal Display) controller/
driver. When the proper voltage is applied to LCD power supply in-
put pins (VLC1–VLC3) and data are set in timer control register
(W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the
LCD controller/driver automatically reads the display data and con-
trols the LCD display by setting duty and bias.
4 common signal output pins and 32 segment signal output pins
can be used to drive the LCD. By using these pins, up to 128 seg-
ments (when 1/4 duty and 1/3 bias are selected) can be controlled
to display. The LCD power input pins (VLC1–VLC3) are also used as
pins SEG0–SEG2. When SEG0–SEG2 are selected, the internal
power (VDD) is used for the LCD power.
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select the
proper display method for the LCD panel being used.
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
Table 11 Duty and maximum number of displayed pixels
Duty Maximum number of displayed pixels Used COM pins
1/2 64 segments
COM0, COM1 (Note)
1/3 96 segments
COM0–COM2 (Note)
1/4 128 segments
COM0–COM3
Note: Leave unused COM pins open.
(2) LCD clock control
The LCD clock is determined by the timer LC count source selec-
tion bit (W62), timer LC control bit (W63), and timer LC.
Accordingly, the frequency (F) of the LCD clock is obtained by the
following formula. Numbers (➀ to ➂) shown below the formula cor-
respond to numbers in Figure 33, respectively.
• When using the prescaler output (ORCLK) as timer LC count
source (W62=“1”)
1
1
F = ORCLK ✕ _{LC + 1} ✕
2
➀
➁
➂
• When using the bit 4 of timer 5 as timer LC count source (W62=“0”)
1
1
F = T54 ✕ _{LC + 1} ✕ ₂
➀
➁
➂
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
F
Frame frequency =
(Hz)
n
Frame period =
n
(s)
F
F: LCD clock frequency
1/n: Duty
T 54
ORCLK
W 62
0
1
➀
(Note)
W 63
➁
➂
0
Timer LC (4)
1
1/2
Reload register RLC
(4)
(TLCA) _(TLCA)
Register A
Note: Count source is stopped by setting “0” to this bit.
Fig. 33 LCD clock control circuit structure
LCD clock
Rev.3.00 Aug 06, 2004 page 46 of 136
REJ03B0043-0300Z