4554 Datasheet, PDF (28/138 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4554 Group
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 inter-
rupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13 INT0 pin input control bit (Note 2)
Interrupt valid waveform for INT0 pin/
I12
return level selection bit (Note 2)
I11 INT0 pin edge detection circuit control bit
INT0 pin Timer 1 count start synchronous
I10
circuit selection bit
at reset : 00002
at power down : state retained
R/W
TAI1/TI1A
0
INT0 pin input disabled
1
INT0 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Interrupt control register I2
I23 INT1 pin input control bit (Note 2)
Interrupt valid waveform for INT1 pin/
I22
return level selection bit (Note 2)
I21 INT1 pin edge detection circuit control bit
INT1 pin Timer 3 count start synchronous
I20
circuit selection bit
at reset : 00002
at power down : state retained
0
INT1 pin input disabled
R/W
TAI2/TI2A
1
INT1 pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI1
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI1
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 3 count start synchronous circuit not selected
1
Timer 3 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set.
Rev.3.00 Aug 06, 2004 page 28 of 136
REJ03B0043-0300Z