HD404459 Datasheet, PDF (90/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

^{HD404459 Series}
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMRA write
Yes
IFS = 1?
No
Normal
termination
Transmit clock
error processing
Transmit clock error detection flowchart
State
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK pin
(input)
SMRA
write
IFS
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMRA is written,
IFS is set.
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedures
Figure 70 Transmit Clock Error Detection
88