HD404459 Datasheet, PDF (89/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

HD404459 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected (figure 70).
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 0) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
again entered. After the transfer is completed and IFS is reset, writing to serial mode register A (SMRA:
$005) then changes the state from transfer to STS wait. However, during the time the serial interface was in
the transfer state with the serial interrupt request flag (IFS: $023, bit 0) being set again, the error can be
detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.
• Serial interrupt request flag (IFS: $023, bit 0) set: For the serial interface, if the state is changed from
transfer state to another by writing to serial mode register A (SMRA: $005) or executing the STS
instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $023,
bit 0) is not set. To set the serial interrupt request flag (IFS: $023, bit 0), a serial mode register A
(SMRA: $005) write or STS instruction execution must be programmed to be executed after confirming
that the SCK pin is at 1, that is, after executing the input instruction to port R4.
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