HD404459 Datasheet, PDF (85/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

HD404459 Series
The output level of the SO pins is undefined until the first data of each serial interface is output after MCU
reset, or until the output level control in idle states is performed.
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by the STS instruction and is incremented at the rising edge of the transmit clock for the serial interface.
When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the
octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 0) for serial interface is set, and
the transfer stops.
When the prescaler output is selected as the transmit clock of the serial interface, the transmit clock
frequency is selected as 4t_cyc to 8192t_cyc by setting bits 0 to 2 (SMRA0–SMRA2) of serial mode register A
(SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) (table 29).
Table 28 Serial Interface Operating Mode
SMRA
Bit 3
1
PMRA
Bit 1
0
1
Bit 0
0
1
0
1
Operating Mode
Continuous clock output mode
Transmit mode
Receive mode
Transmit/receive mode
Table 29 Serial Transmit Clock (Prescaler Output)
SMRB
Bit 0
0
SMRA
Bit 2
0
Bit 1
0
1
1
0
1
0
0
1
1
0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
Prescaler Division Ratio
÷ 2048
÷ 512
÷ 128
÷ 32
÷8
÷2
÷ 4096
÷ 1024
÷ 256
÷ 64
÷ 16
÷4
Transmit Clock Frequency
4096t_cyc
1024t_cyc
256t_cyc
64t_cyc
16t_cyc
4t _cyc
8192t_cyc
2048t_cyc
512t_cyc
128t_cyc
32t_cyc
8t _cyc
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