HD404459 Datasheet, PDF (21/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

HD404459 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Timer A or Timer B or Timer C or
Control Bit
INT₀
INT₁
Timer D INT₂
INT₃
Serial
Wakeup
IE
1
1
1
1
1
1
1
IF0 · IM0
1
0
0
0
0
0
0
IF1 · IM1
*
1
0
0
0
0
0
IFTD · IMTD *
*
1
0
0
0
0
IFTA · IMTA *
*
*
1
0
0
0
+ IF2 · IM2
IFTB · IMTB *
*
*
*
1
0
0
+ IF3 · IM3
IFTC · IMTC *
*
*
*
*
1
0
+ IFS · IMS
IFWU · IMWU *
*
*
*
*
*
1
Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
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