HD404459 Datasheet, PDF (87/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

HD404459 Series
• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02 and
12) increments the octal counter, shifts the serial data register (SRL: $006, SRU: $007), and enters the
serial interface in transfer state. However, note that if continuous clock output state is selected in
internal clock mode, the serial interface does not enter transfer state but enters continuous clock output
state (17).
The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04
and 14) in transmit clock wait state.
• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05 and 15), transmit clock wait state is entered. When eight clocks are input, transmit clock
wait state is entered (03) in external clock mode, or STS wait state is entered (13) in internal clock
mode. In internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register A (SMRA: $005) (06 and 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 0) is set
by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
Output Level Control in Idle States: When the serial interface is in STS instruction wait state and
transmit clock wait state, the output of serial output pin SO can be controlled by setting bit 1 (SMRB1) of
serial mode register B (SMRB: $028) to 0 or 1. See figure 69 for an output level control example of the
serial interface. Note that the output level cannot be controlled in transfer state.
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