HD404459 Datasheet, PDF (11/122 Pages) Renesas Technology Corp – 4-bit HMCS400-series microcomputers

HD404459 Series
Interrupt control bits area
Bit 3
Bit 2
IM0
0
(IM of INT₀)
IF0
(IF of INT₀)
1
IMTD
(IM of timer D)
IFTD
(IF of timer D)
2
IMTB
(IM of timer B)
IFTB
(IF of timer B)
IMWU
IFWU
3 _{(IM of wakeup) (IF of wakeup)}
Bit 1
RSP
(Reset SP bit)
IM1
(IM of INT₁)
IMTA
(IM of timer A)
IMTC
(IM of timer C)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
$000
$001
IFTA
(IF of timer A)
$002
IFTC
(IF of timer C)
$003
Register flag area
Bit 3
DTON
32 (Direct transfer
on flag)
RAME
33 (RAM enable
flag)
Bit 2
CMSF
(Comparator
start flag)
Not used
34
IM3
(IM of INT₃)
IF3
(IF of INT₃)
35
Not used
Not used
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
IM2
(IM of INT₂)
IMS
(IM of serial)
Bit 0
LSON
(Low speed
on flag)
ICSF
(Input capture
status flag)
IF2
(IF of INT₂)
IFS
(IF of serial)
$020
$021
$022
$023
IF: Interrupt request flag
IM: Interrupt mask
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
CMSF
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for CMSF during comparator
operation. DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes undefined.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9