H8S78 Datasheet, PDF (9/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Main Revisions for This Edition
Item
3.4 Memory Map in
Each Operating Mode
Figure 3.2 Memory
Map for H8S/2378 and
H8S/2378R (2)
Page
79
Revision (See Manual for Details)
Figure amended
ROM: 512 kbytes
RAM: 32 kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
H'000000
ROM: 512 kbytes
RAM: 32 kbytes
Mode 5
(User boot mode)
H'000000
ROM: 512 kbytes
RAM: 32 kbytes
Mode 7
(Single-chip activation
expanded mode,
with on-chip ROM enabled)
H'000000
On-chip ROM
On-chip ROM
On-chip ROM
Figure 3.7 Memory 84
Map for H8S/2374 and
H8S/2374R (1)
Figure 3.15 Memory 92
Map for H8S/2370 and
H8S/2370R (2)
6.7.11 Byte Access 230
Control
Figure 6.51 Example
of DQMU and DQML
Byte Control
6.9.2 Pin States in
268
Idle Cycle
Table 6.12 Pin States
in Idle Cycle
7.3.7 DMA Terminal 306
Control Register
(DMATCR)
H'080000
Figure amended
H'080000
H'080000
H'FF4000
H'FFC000
On-chip RAM/
external address
space*1
Figure amended
H'FF4000
H'FFC000
On-chip RAM*³
H'FF4000
H'FF8000
H'FFC000
Reserved area*⁴
On-chip RAM/
external address
space*1
Figure amended
H'FF4000
H'FF8000
H'FFC000
Reserved area*⁴
On-chip RAM^*5
H'FF4000
H'FF8000
H'FFC000
Reserved area*⁴
On-chip RAM/
external address
space*3
This LSI
(Address shift size set to 8 bits)
64-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
CS2 (RAS)
CS3 (CAS)
RAS
CAS
Table amended
Pins
EDACKn (n = 3, 2)
Pin State
High
Description amended
… The TEND pin is available only for channel B in short
address mode.
Rev.7.00 Mar. 18, 2009 page vii of lxvi
REJ09B0109-0700