H8S78 Datasheet, PDF (709/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 12 Programmable Pulse Generator (PPG)
12.4 Operation
Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
DDR
NDER
Q
Output trigger signal
Pulse output pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.2 Overview Diagram of PPG
Rev.7.00 Mar. 18, 2009 page 641 of 1136
REJ09B0109-0700