H8S78 Datasheet, PDF (333/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 6 Bus Controller (BSC)
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Normal space write Normal space read
ICIS2
0
1
ICIS1
⎯
⎯
ICIS0
⎯
⎯
DRAM^*/continuous
0
synchronous DRAM
space read
1
⎯
⎯
⎯
⎯
DRAM/continuous Normal space read
0
synchronous DRAM^*
space write
1
⎯
⎯
⎯
⎯
DRAM^*/continuous
0
synchronous DRAM
space read
1
⎯
⎯
⎯
⎯
Note: * Not supported by the H8S/2378 Group.
DRMI
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IDLC
⎯
0
1
⎯
0
1
⎯
0
1
⎯
0
1
Idle cycle
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
Rev.7.00 Mar. 18, 2009 page 265 of 1136
REJ09B0109-0700