H8S78 Datasheet, PDF (1145/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 26 Electrical Characteristics
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
Tp
t_AD
Tr
Tc1
Tc2
t_AD
t_AS3
t_PCH2
t_AH1
t_CSD2
t_AS2
t_AH2
t_CASD1
t_CSD3
t_CASD1
t_CASW1
t_OED1
t_AC1
t_OED1
Read HWR
D15 to D0
t_AA3
t_AC4
t_RDS2 t_RDH2
OE, RD
Write _HWR
D15 to D0
t_WRD2
t_WCS1 t_WCH1
t_WRD2
t_WDD
t_WDS1
t_WDH2
AS
DACK0, DACK1
EDACK2, EDACK3
t_DACD1
t_EDACD1
t_DACD2
t_EDACD2
Note: _{DACK and EDACK timing: when DDS = 0 and EDDS = 0}
RAS timing: when RAST = 0
Figure 26.14 DRAM Access Timing: Two-State Access
Rev.7.00 Mar. 18, 2009 page 1077 of 1136
REJ09B0109-0700