H8S78 Datasheet, PDF (870/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 16 I²C Bus Interface 2 (IIC2) (Option)
16.6 Bit Synchronous Circuit
In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization.
Figure 16.18 shows the timing of the bit synchronous circuit and table 16.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
SCL
VIH
Internal SCL
Figure 16.18 Timing of the Bit Synchronous Circuit
Table 16.4 Time for monitoring SCL
CKS3
0
1
CKS2
0
1
0
1
Time for monitoring SCL
7.5 tcyc
19.5 tcyc
17.5 tcyc
41.5 tcyc
Rev.7.00 Mar. 18, 2009 page 802 of 1136
REJ09B0109-0700