H8S78 Datasheet, PDF (842/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 16 I²C Bus Interface 2 (IIC2) (Option)
16.3 Register Descriptions
The I²C bus interface has the following registers.
• I²C bus control register A_0 (ICCRA_0)
• I²C bus control register B_0 (ICCRB_0)
• I²C bus mode register_0 (ICMR_0)
• I²C bus interrupt enable register_0 (ICIER_0)
• I²C bus status register_0 (ICSR_0)
• I²C bus slave address register_0 (SAR_0)
• I²C bus transmit data register_0 (ICDRT_0)
• I²C bus receive data register_0 (ICDRR_0)
• I²C bus shift register_0 (ICDRS_0)
• I²C bus control register A_1 (ICCRA_1)
• I²C bus control register B_1 (ICCRB_1)
• I²C bus mode register_1 (ICMR_1)
• I²C bus interrupt enable register_1 (ICIER_1)
• I²C bus status register_1 (ICSR_1)
• I²C bus slave address register_1 (SAR_1)
• I²C bus transmit data register_1 (ICDRT_1)
• I²C bus receive data register_1 (ICDRR_1)
• I²C bus shift register_1 (ICDRS_1)
Rev.7.00 Mar. 18, 2009 page 774 of 1136
REJ09B0109-0700