H8S78 Datasheet, PDF (869/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 16 I²C Bus Interface 2 (IIC2) (Option)
16.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each
interrupt request.
Table 16.3 Interrupt Requests
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Detection
Arbitration Lost
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TDRE=1) • (TIE=1)
(TEND=1) • (TEIE=1)
(RDRF=1) • (RIE=1)
(STOP=1) • (STIE=1)
{(NACKF=1)+(AL=1)} • (NAKIE=1)
Interrupt exception handling is performed when the interrupt conditions listed in table 16.3 are set
to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources
should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing
transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In
particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is
cleared again, an extra byte of data may be transmitted.
Rev.7.00 Mar. 18, 2009 page 801 of 1136
REJ09B0109-0700