H8S78 Datasheet, PDF (142/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 3 MCU Operating Modes
• H8S/2377, H8S/2377R, H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R
Bit Bit Name Initial Value R/W
7, 6 ⎯
All 1
R/W
5, 4 ⎯
All 0
R/W
3
FLSHE
0
R/W
2⎯
0
⎯
1 EXPE
⎯
R/W
0 RAME
1
R/W
Descriptions
Reserved
The initial value should not be modified.
Reserved
The initial value should not be modified.
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read from and written to. If this bit is cleared to
0, the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are maintained. This bit should be written to
0 in other than flash memory version.
0: Flash memory control registers are not selected for
area H'FFFFC8 to H'FFFFCB
1: Flash memory control registers are selected for
area H'FFFFC8 to H'FFFFCB
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4, this bit is fixed at 1 and cannot
be modified. In modes 3 and 7, this bit can be read
from and written to.
Writing of 0 to this bit when its value is 1 should only
be carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev.7.00 Mar. 18, 2009 page 74 of 1136
REJ09B0109-0700