H8S78 Datasheet, PDF (341/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 6 Bus Controller (BSC)
External space read
T₁
T₂
φ
SDRAMφ
Address bus
Data bus
Precharge-sel
RAS
CAS
WE
CKE
DQMU, DQML
BREQ
BACK
BREQO
External bus released state
Row
address
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
CPU
cycle
NOP
PALL NOP
NOP
[1]
[2]
[3]
[4]
[5]
[8]
[6]
[7]
[9]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
Note: In the H8S/2373 Group, the synchronous DRAM interface is not supported.
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface
Rev.7.00 Mar. 18, 2009 page 273 of 1136
REJ09B0109-0700