H8S78 Datasheet, PDF (325/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 6 Bus Controller (BSC)
φ
Address bus
Precharge-sel
RAS
CAS
WE
Continuous synchronous
DRAM space read
External space read
Continuous synchronous
DRAM space read
T_p
T_r
T_c1 T_cl
T_c2
T₁
T₂
T₃
T_i
T_i
T_c1 T_Cl
T_c2
Column Row
address address
Column address 1
Row
address
External address
External address
Column address 2
CKE
DQMU, DQML
RD
HWR, LWR
Data bus
High
High
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 1, CAS Latency 2)
Rev.7.00 Mar. 18, 2009 page 257 of 1136
REJ09B0109-0700