H8S78 Datasheet, PDF (371/1208 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Bit Bit Name Initial Value R/W
2
DTIE1A
0
R/W
1
DTIE0B
0
R/W
0
DTIE0A
0
R/W
Section 7 DMA Controller (DMAC)
Description
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE1 bit is cleared to 1
when DTIE1A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 1 is interrupted. If the
DTME0 bit is cleared to 0 when DTIE0B = 1, the
DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or DTC
when transfer ends. If the DTE0 bit is cleared to 0
when DTIE0A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
Rev.7.00 Mar. 18, 2009 page 303 of 1136
REJ09B0109-0700