M16C6C Datasheet, PDF (88/94 Pages) Renesas Technology Corp – RENESAS MCU

M16C/6C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
CSi
td(BCLK-CS)
30ns(max.)
tcyc
V_CC1 = V_CC2 = 3 V
th(BCLK-CS)
0ns(min.)
ADi
BHE
ALE
RD
DBi
Write timing
BCLK
CSi
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
th(RD-AD)
0ns(min.)
Hi-Z
td(BCLK-RD)
30ns(max.)
tac2(RD-DB)
{(n+0.5) × t cyc-60}ns(max.)
tac2(RD-DB)
{(n+0.5) × t cyc-60}ns(max.)
th(BCLK-RD)
0ns(min.)
tsu(DB-RD)
50ns(min.)
th(RD-DB)
0ns(min.)
td(BCLK-CS)
30ns(max.)
tcyc
th(BCLK-CS)
0ns(min.)
ADi
BHE
ALE
WR
DBi
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-WR)
30ns(max.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
th(BCLK-WR)
0ns(min.)
Hi-Z
td(BCLK-DB)
40ns(max.)
th(BCLK-DB)
0ns(min.)
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
th(WR-DB)
(0.5 × tcyc-10)ns(min.)
1
tcyc = _f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.19 Timing Diagram
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
REJ03B0277-0100 Rev.1.00 Jul.15, 2009
Page 86 of 90